CMOS INVERTER CIRCUIT
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characteristics of the inverter circuit are thoroughly understood, the results can be extended to the design of logic gates and other more complex circuits.
The basic CMOS inverter as shown, it utilizes two matched enhancement-type MOSFETs: one pMOS and one nMOS. The Body of each device is connected to its source and thus no body effect arises.
For Ideal CMOS Inverter
nMOS & pMOS only operate in either Triode or Cut off 2 Regions
For Non-Ideal CMOS Inverter
when Vin is at logic 0 level (Vin = 0V)
nMOS:
VGSn = 0V (VGSn less than Vtn)
nMOS OFF
pMOS:
VSGp = VDD (VSGp more than Vtp and VDSp less than VSGp - Vtp)
pMOS Triode Region
IDn = IDp = 0
when Vin is at logic 1 level (Vin = VDD)
nMOS:
VGSn = VDD (VGSn more than Vtn and VDSn less than VGSn - Vtn)
nMOS Triode Region
pMOS:
VSGp = VDD-VDD = 0V (VSGp less than Vtp)
pMOS OFF
IDn = IDp = 0
VGSn = Vin
VGSp = - (VDD - Vin)
VDSn = Vout
VDSp = - (VDD - Vout)
