Random Access Memory (RAM)

Dynamic Random Access Memory (DRAM)

DRAM stores its bit of information as chrage on the cell capacitor

The gate of the transistor is connected to the word line, and its source (drain) is connected to the bit line.

When storing a 1, the capacitor is charged to (Vdd-Vto)

When storing a 0, the capacitor is discharged to 0V

DRAM

1-T DRAM write 0

SRAM

Static Random Access Memory (SRAM)

Each cell contains two inverters. Each cell design is basically two cross coupled inverters.

Most SRAM are now CMOS with PMOS load transistor. Since CMOS inverters have low static power dissipation.

Each CMOS SRAM cell comprises 6 transistors.